1. Field of the Invention
The present invention relates to a semiconductor circuit arrangement having a circuit element which is formed in an integrated manner in a semiconductor substrate of a first conductivity type and has at least one control terminal and a first and second electrode terminal, the first electrode terminal being formed by a terminal well—embedded within the semiconductor substrate—of a second conductivity type opposite to the first conductivity type and a sub-well region of the second conductivity type which is situated within the terminal well but is doped more highly than the terminal well, and also to a method for producing such a semiconductor circuit arrangement
2. Description of the Related Art
Known examples of such semiconductor circuit arrangements are MOS tetrodes and MOS pentodes having a plurality of control terminals, in particular having at least two gate terminals, namely a high-frequency gate and at least one control gate, which are fabricated either as individual components or in highly integrated form on a semiconductor substrate by means of VLSI technology steps (VLSI=very large scale integration). A suitability for supply voltages of 12 V or more is demanded in particular when such MOS tetrodes are used in automotive engineering. The modern CMOS process fabrication methods are generally only designed for the fabrication of semiconductor circuits for supply voltages of <5 V and are not readily suitable for the fabrication of semiconductor circuits with higher supply voltage ranges. Essential technological reasons for this reside, inter alia, in the excessively small gate oxide thickness and also in an excessively low drain-well breakdown voltage in the semiconductor circuits which are fabricated in modern standard CMOS processes and are therefore not readily suitable for the fabrication of MOS tetrodes and MOS pentodes with supply voltages of 12 V or more.